The invention relates to semiconductor product test technology, and more particularly, to a method and system of SBC/SBL (Statistic BIN Control/Statistic BIN Limit) rule verification for semiconductor device/product testing.
A conventional semiconductor factory typically includes fabrication tools required to process semiconductor wafers for a particular purpose, such as photolithography, chemical-mechanical polishing, or chemical vapor deposition. During manufacture, the semiconductor wafer passes through a series of process steps performed by various fabrication tools. For example, in the production of an integrated semiconductor product, the semiconductor wafer passes through up to 600 process steps. The cost of such automated production is greatly influenced by how efficiently the manufacturing process can be monitored or controlled, such that the ratio of defect-free products to the overall number of products manufactured (i.e., yield ratio) achieves the greatest possible value. The individual process steps, however, are subject to fluctuation and irregularities, which in the worst case may generate a defective number of chips or the entire wafer. Therefore, each individual process step must be carried out as stably as possible to ensure an acceptable yield after the completed processing of a wafer.
Circuit probing (CP) testing systems/methods have been used in a variety of semiconductor fabrication processes for acquiring yield data. A test program is provided by a user or operator for a CP test on a particular semiconductor product. The test program describes a test flow including multiple test items, and the test items are typically optimally arranged to reduce CP test time. A CP test station then follows the predefined test flow to sequentially probe all dies on a wafer to determine whether a die is good or bad. After completing the entire CP test, results of test attributes such as yield values, quantities of good dies, repairable dies, power short dies and the like, for wafers, wafer lots or semiconductor products, are acquired. Test-results are subsequently carried into SBC/SBL rules to generate final advisories such as acceptance, scrap, hold for analysis, downgrade and the like, for wafers, wafer lots or semiconductor products.
Prior to a CP test, SBC/SBL rules are verified and negotiated to ensure the benefit will not be damaged. For example, a more restrictive SBC/SBL rule causes more scrapping and requires further verification. Conventionally, operators spend much time communicating various SBC/SBL rules, and this labor-intensive management method severely hinders efficiency.